1. Field of the Invention
The present invention generally relates to a chip test method, and more particularly to an RF chip test method.
2. Description of the Prior Art
Chip tests are typically performed during semiconductor chip production processes to ensure the quality of electrical characteristics of the semiconductor chips being fabricated. FIG. 1 is a schematic diagram corresponding to a prior-art chip test process. A chip 50 is disposed within a chip socket 110. The chip 50 has at least one non-RF pin 51 and at least one RF pin 52. The chip socket 110 is disposed on a test board 120. The test board 120 has at least one test circuit. The chip socket 110 has a plurality of conductive elements 130. The press mechanism 70 moves downward to make the conductive elements 130 contact the non-RF pin 51 and the RF 52 pin tightly.
Generally, when performing the chip test process of the chip 50, a DC open/short test will be performed first to ensure the contact condition between the non-RF pin 51 and the conductive elements 130. The electric resistance of the non-RF pin 51 is measured by a DC source so as to ensure the properties of ESD protecting diode of the chip 50. When performing the DC open/short test, the direct current is provided by a digital power source (DPS) or a precise measure unit (PMU), and the electric resistance is calculated using the measured voltage.
The chip test process of the RF pin 52 is a high frequency analog test. When the RF pin 52 and the chip socket 110 has a bad contact condition, high frequency parasitic capacitance and parasitic inductance will be formed between the RF pin 52 and the chip socket 110. Moreover, the chip test result of the RF pin 52 will be affected by the high frequency parasitic capacitance and parasitic inductance. Therefore, the contact condition between the RF pin 52 and the chip socket 110 should be ensured before the high frequency analog test of the RF pin 52.
In the conventional chip test machine, the RF pin 52 is connected to an RF measuring instrument. The RF pin 52 is not connected to a DC source (DPS/PMU) that is able to perform the DC open/short test. In order to perform the DC open/short test of the RF pin 52, RF relays must be disposed on the test board 120 for switching the RF pin 52 to the DC source (DPS/PMU) or the RF measuring instrument. When performing the DC open/short test, the RF pin 52 is connected to the DC source (DPS/PMU). When performing the high frequency analog test, the RF pin 52 is connected to the RF measuring instrument.
However, there are some disadvantages associated with the RF relays. The RF relays have to use the space of the test board 120, the cost of the RF relay is high, the working life of the RF relay is short, and it is necessary to change RF relays frequently in mass production contexts. Therefore, the cost of the RF chip test is increased.
As a consequence of RF relays increasing the high frequency parasitic capacitance and parasitic inductance of the test circuit of the test board 120, chip test results are adversely affected by high frequency parasitic capacitance and parasitic inductance. Therefore, the test result of the RF chip is not stable.
Besides, in order to make the chip test result stable, the total chip test time is increased because it is necessary to add delay time after switching the test circuits by the RF relays. Therefore, the efficiency of the RF chip test process is low.
For reasons including the disadvantages of the prior art mentioned above, there is a need to propose a novel RF chip test method. Use of such an RF chip test method should vitiate the need to use RF relays to test the contact condition between RF pins and the chip socket.